////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 1999-2008 Easics NV.
// This source file may be used and distributed without restriction
// provided that this copyright statement is not removed from the file
// and that any derivative work contains the original copyright notice
// and the associated disclaimer.
//
// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
// OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
// WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
//
// Purpose : synthesizable CRC function
// * polynomial: x^6 + x^1 + 1
// * data width: 15
//
// Info : tools@easics.be
// http://www.easics.com
////////////////////////////////////////////////////////////////////////////////
module crc_check(iRaw,iCRC,oRaw_CRC,oValid);
input [14:0] iRaw;
input [5:0] iCRC;
output reg [5:0] oRaw_CRC;
output reg oValid;
reg [14:0] raw_data_flipped;
reg [5:0] crc_flipped;
always @(*) begin
raw_data_flipped[00] <= iRaw[14];
raw_data_flipped[01] <= iRaw[13];
raw_data_flipped[02] <= iRaw[12];
raw_data_flipped[03] <= iRaw[11];
raw_data_flipped[04] <= iRaw[10];
raw_data_flipped[05] <= iRaw[09];
raw_data_flipped[06] <= iRaw[08];
raw_data_flipped[07] <= iRaw[07];
raw_data_flipped[08] <= iRaw[06];
raw_data_flipped[09] <= iRaw[05];
raw_data_flipped[10] <= iRaw[04];
raw_data_flipped[11] <= iRaw[03];
raw_data_flipped[12] <= iRaw[02];
raw_data_flipped[13] <= iRaw[01];
raw_data_flipped[14] <= iRaw[00];
crc_flipped[0] <= iCRC[5];
crc_flipped[1] <= iCRC[4];
crc_flipped[2] <= iCRC[3];
crc_flipped[3] <= iCRC[2];
crc_flipped[4] <= iCRC[1];
crc_flipped[5] <= iCRC[0];
end
always @(*) begin
oRaw_CRC = nextCRC6_D15(raw_data_flipped,6'd0);
if(~crc_flipped == oRaw_CRC) oValid = 1;
else oValid = 0;
end
function [5:0] nextCRC6_D15;
input [14:0] Data;
input [5:0] crc;
reg [14:0] d;
reg [5:0] c;
reg [5:0] newcrc;
begin
d = Data;
c = crc;
newcrc[0] = d[12] ^ d[10] ^ d[6] ^ d[5] ^ d[0] ^ c[1] ^ c[3];
newcrc[1] = d[13] ^ d[12] ^ d[11] ^ d[10] ^ d[7] ^ d[5] ^ d[1] ^ d[0] ^ c[1] ^ c[2] ^ c[3] ^ c[4];
newcrc[2] = d[14] ^ d[13] ^ d[12] ^ d[11] ^ d[8] ^ d[6] ^ d[2] ^ d[1] ^ c[2] ^ c[3] ^ c[4] ^ c[5];
newcrc[3] = d[14] ^ d[13] ^ d[12] ^ d[9] ^ d[7] ^ d[3] ^ d[2] ^ c[0] ^ c[3] ^ c[4] ^ c[5];
newcrc[4] = d[14] ^ d[13] ^ d[10] ^ d[8] ^ d[4] ^ d[3] ^ c[1] ^ c[4] ^ c[5];
newcrc[5] = d[14] ^ d[11] ^ d[9] ^ d[5] ^ d[4] ^ c[0] ^ c[2] ^ c[5];
nextCRC6_D15 = newcrc;
end
endfunction
endmodule
Verilog