PCB

BiSS-C Interface Board

Version 1.0 (May 2020)

Version 2.0 (Dec 2020)

Version 3.0 (Mar 2022)

Version 1.0 (Feb 2022)

Bottom Side is fully assembled by JLCPCB

Assembled Photo

Issues

Version 2

BiSS-C Interface Board

Version 1.0 (May 2020)

Version 1

Version 2.0 (Dec 2020)

Version 2

Version 3.0 (Mar 2022)

Revise J9 Adapter (Removed as deprecate PIO method)

Order Stencil (Design can be hand soldered easily)

Implement CAN (Not needed for BiSS)

Move FPGA due to height restriction

Removed J9 Connection

Move RJ45 top side

Uses SPIA Bus

4x Trigger Pin, Trigger 1,2 has LPF on delfino side

Larger Fuse footprint (Use Original Size)

Design File

BiSS Interface Board v22.1 EasyEDA.zip

164.0KB

Schematic

AABBCCDD1122334455TITLE:BiSS Interface BoardREV:22.1Date:2022-03-20Sheet:1/1Drawn By:Boon JunCompany:Monash MotorsportF28379D-BOOSTER-1H13V31P322P193P184P675P1116P607P228P1059P10410J1J35V21GND22A1423AC324AB325AA326AC227AB228AA229AA030J4J2P2911P12512P12413P5914P5815RST16P12217P12318P6119GND20D231D132P1633P2434P535P436P337P238P139P040LAUNCHXL-F28379D InterfaceSRV05-4-P-T7D2123456SRV05-4-P-T7D1123456ESD Protection5V5VGNDGNDR-RJ45R10P-B000RJ112345678S10S9R-RJ45R10P-B000RJ212345678S10S9SN65HVD179DU3VCC1R2D3GND4Y5Z6B7A8SN65HVD179DU1VCC1R2D3GND4Y5Z6B7A85V5VGNDGNDGNDGNDGNDMA_1_PSLO_1_NSLO_1_PMA_1_NMA_2_NSLO_2_PSLO_2_NMA_2_P120ΩR210nFC210nFC4120ΩR4100nFC1100nFC3SLO_1_PSLO_1_NMA_1_PMA_1_NMA_2_NMA_2_PSLO_2_NSLO_2_P5V5VGNDGNDGNDGNDTransceiverI/OmSMD075-13.2VF1mSMD075-13.2VF2JP1JP2GNDGNDGND5V5V560ΩR11kΩR3SLO_1SLO_2MA_1MA_2SLO_1SLO_21kΩR6560ΩR5GNDGNDSLO_1_3V3SLO_2_3V3Level ShifterFPGASPI_CSSPI_MISOSPI_MOSISPI_SCLKTRIGGER_2TRIGGER_1100R7100R8https://au.rs-online.com/web/p/line-interface-ics/6608855SLO_2_PMA_2_PSLO_2_NMA_2_NSLO_1_NMA_1_PMA_1_NSLO_1_PSPI_SCLKSPI_MISOSPI_MOSISPI_CSSLO_2_3V3MA_2MA_1SLO_1_3V3TRIGGER_2TRIGGER_1JP3JP4SLO_1_3V3MA_1mSMD075-13.2VF3XH-2AJ11122GND5VExt PowerCMOD S7U21234567891617181920212223VU24GND25262728293031AN32AN33404142434445464748J3J4J1J2CMOD S7 FPGA100R9100R10TRIGGER_3TRIGGER_4TRIGGER_4TRIGGER_3

PCB

PCB Order Instruction (BiSSv22.1)

SPI Data Logger PCB

Version 1.0 (Feb 2022)

Design File

Logger Board PCB EasyEDA.zip

304.6KB

Schematic

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PCB

Manufacturing Files

BOM_PCB_ESP32-LOGGER_2022-02-08.csv

6.3KB

Gerber_PCB_ESP32-LOGGER.zip

155.3KB

PickAndPlace_PCB_ESP32-LOGGER_2022-02-08.csv

16.3KB

Bottom Side is fully assembled by JLCPCB

PCB Order Instruction

Assembled Photo

Issues

Booster Board Expansion IO is flipped 180

The board can be setup to be used on SPIB bus instead

GPIO12 Pullup Resistor R33 is at top side instead of bottom

Version 2

Add mounting options

Reorganise components for final packaging