EXPECT SIMILAR ANALYSIS WITH BETTER QUALITY IN FUTURE
Context
Ch1 = Yellow
Ch2 = Blue
Ch1 is running on better probe than Ch2, Ch2 can't do high frequency so it can't provide better "square" feature of the signal.
The test is perform on gwinstek GDS-3154 150MHz, 5GS/s oscilloscope
4MHz Test
BiSS CLK (PIN47 - GPIO65)
Rise time & fall time
DS0002.png
ePWM HRPWM (PIN40 - GPIO0)
Rise time & fall time
DS0003.png
GPIO124 (PIN13) to SPI CLK Reaction Time
DS0006.png
FPGA PWM (4.16667MHz using Pin JB[0])
RS422 & CLK
DS0007.png (Pos)
DS0008.png (Neg)
DS0009.png (Delta Pos)
(Blue = RS422)
RS422 & Data
DS0010.png (Delta Pos)
DS0011.png (Pos)
DS0012.png (Neg)
Prob Same Pin
DS0004.png
DS0005.png (Cheaper Prob)
Scope Data @ 4MHz (ACK - START) (Delfino)
DS0014.png
Scope Data @ 4MHz (ACK - START) (RS422(CLK) , Delfino(Data))
DS0015.png
Scope Data @ 4MHz (ACK - START) (RS422(CLK) , RS422(Data))
DS0016.png
8MHz Test
Function Generator
DS0013.png
BiSS CLK (PIN47 - GPIO65)
Rise time & fall time
DS0021.png
DS0022.png
DS0023.png
ePWM HRPWM (PIN40 - GPIO0)
Rise time & fall time
DS0024.png
GPIO124 (PIN13) to SPI CLK Reaction Time
DS0025.png
DS0026.png
FPGA PWM (8.333MHz using Pin JB[1])
Scope Data @ 8MHz (ACK - START)
DS0017.png (CLK - Good Probe)
DS0018.png (Data - Good Probe)
DS0019.png (Delta) (Data - Good Probe)
DS0020.png (Delta) (CLK - Good Probe)
RS422 & CLK
DS0027.png
RS422 & Data
Blue - RS422 SLO line
Yellow - Delfino SPISOMI
DS0028.png
Differential Line
DS0029.png (CLK)
DS0030.png (Data)
One frame of data
DS0031.png
DS0032.png
DS0033.png
DS0034.png
6MHz
Scope Data @ 6MHz (ACK - START)
DS0035.png
Packing List