Reference Guide
You are here:: Digilent Documentation / Reference / Programmable Logic / Cmod S7 / Cmod S7 Reference ManualThe Digilent Cmod S7 is a small, 48-pin DIP form factor board built around a Xilinx Spartan 7 FPGA. 32 FPGA digital I/Osignals, 2 FPGA analog input signals, an external power input rail, and ground are routed to 100-mil-spaced through-holepins, making the Cmod S7 well suited for use with solderless breadboards. At just 0.7” by 3.05” inches, it can be loaded in astandard socket and used in embedded systems. The board also includes a programming ROM, clock source, USBprogramming and data transfer circuit, power supplies, LEDs, and buttons. Xilinx Spartan-7 FPGA (XC7S25-1CSGA225C)3,650 slices containing four 6-input LUTs and 8 flip-flopsCmod S7 Reference ManualFeaturesTable of Contents
Name
URL
File
Catogory
Tag
ds189-spartan-7-data-sheet.pdf
Cmod S7
FPGA
reference-digilentinc-com-reference-programmable-logic-cmod-s7-reference-manual.pdf
Cmod S7
FPGA
Settings
Constraint File
Pin Pullup:
set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 PULLTYPE PULLUP } [get_ports { pio28 }]; #IO_L5P_T0_D06_14 Sch=pio[28]
Verilog
5V Integration
(Not need for Delfino as they run on 5V)
Level Shifer Rated for 20Mbps
1FEATURESZXY PACKAGE(BOTTOM VIEW)ABCD213451918171615141213123456798101120B1B2B4B6B8VB3B5B7A1A2A4A6A8VCCAA3A5A7OEGND1918171615141213123456798101120A1B1A2A4A6A8VCCAA3A5A7B2B4B6B8VCCBB3B5B7OEGNDExposedCenterPadTXS0108Ewww.ti.com.....................................................................................................................................SCES642B–DECEMBER2007–REVISEDSEPTEMBER20088-BITBIDIRECTIONALVOLTAGE-LEVELTRANSLATORFOROPEN-DRAINANDPUSH-PULLAPPLICATIONS•NoDirection-ControlSignalNeeded•IEC61000-4-2ESD(BPort)•MaxDataRates–±8-kVContactDischarge–60Mbps(PushPull)–±6-kVAir-GapDischarge–2Mbps(OpenDrain)•1.2Vto3.6VonAPortand1.65Vto5.5VonBPort(VCCA≤VCCB)•NoPower-SupplySequencingRequired–EitherVCCAorVCCBCanBeRampedFirst•Latch-UpPerformanceExceeds100mAPerJESD78,ClassII•ESDProtectionExceedsJESD22(APort)–2000-VHuman-BodyModel(A114-B)–150-VMachineModel(A115-A)–1000-VCharged-DeviceModel(C101)TERMINALASSIGNMENTS12345DVCCBB2B4B6B8CB1B3B5B7GNDBA1A3A5A7OEAVCCAA2A4A6A8PWPACKAGERGYPACKAGE(TOPVIEW)(TOPVIEW)Theexposedcenterpad,ifused,mustbeconnectedasasecondarygroundorleftelectricallyopen.1Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.PRODUCTIONDATAinformationiscurrentasofpublicationdate.Copyright©2007–2008,TexasInstrumentsIncorporatedProductsconformtospecificationsperthetermsoftheTexasInstrumentsstandardwarranty.Productionprocessingdoesnotnecessarilyincludetestingofallparameters.
6.6ns Delay
Testing: Using Voltage Divider
Timing Performance
UART
SPI
Issues